Silicon-on-Insulator Technology Impacts on SRAM Testing

V
VTS
2000
18th IEEE VLSI Test Symposium (VTS'00)
Abstract - Silicon-on-Insulator Technology Impacts on SRAM Testing

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18th IEEE VLSI Test Symposium (VTS'00)

Montreal, Canada

April 30-May 04

ISBN: 0-7695-0613-5

	ASCII Text	x
	R. Dean Adams, Phil Shephard Iii, "Silicon-on-Insulator Technology Impacts on SRAM Testing," VLSI Test Symposium, IEEE, pp. 43, 18th IEEE VLSI Test Symposium (VTS'00), 2000.

	BibTex	x
	@article{ 10.1109/VTEST.2000.843825, author = {R. Dean Adams and Phil Shephard Iii}, title = {Silicon-on-Insulator Technology Impacts on SRAM Testing}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {2000}, issn = {1093-0167}, pages = {43}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.2000.843825}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Test Symposium, IEEE TI - Silicon-on-Insulator Technology Impacts on SRAM Testing SN - 1093-0167 SP EP A1 - R. Dean Adams, A1 - Phil Shephard Iii, PY - 2000 KW - Fault modeling and simulation KW - Memory testing KW - Silicon On Insulator (SOI) VL - 0 JA - VLSI Test Symposium, IEEE ER -

R. Dean Adams, International Business Machines

Phil Shephard Iii, International Business Machines

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTEST.2000.843825

Silicon-on-insulator (SOI) SRAMs have different characteristics from those fabricated in traditional bulk silicon. Fault models and sensitivities must be considered when testing for SOI manufacturing defects. Circuit details of SOI SRAMs that relate to testing are presented and a new pattern is summarized which covers the related fault models.

Index Terms:

Fault modeling and simulation, Memory testing, Silicon On Insulator (SOI)

Citation:

R. Dean Adams, Phil Shephard Iii, "Silicon-on-Insulator Technology Impacts on SRAM Testing," vts, pp.43, 18th IEEE VLSI Test Symposium (VTS'00), 2000

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