The issue of handling multiple embedded 1149.1- compliant TAP controllers (as part of embedded cores) in a 1149.1-compliant IC, has received significant attention, in recent times. The Hierarchical TAP (HTAP) architecture, previously developed by this author, provides a systematic solution to this problem, by allowing multiple embedded TAP's to share one set of 1149.1-specified test pins on the IC. The HTAP architecture requires an augmented version of the 1149.1-specified TAP - designated the Snoopy TAP (SNTAP) - in the top-level of the design hierarchy, that handles 1149.1-specified TAP functions for the non-TAP'ed parts of the IC, and performs arbitration of the shared IC pins between multiple embedded TAPs. Previously, a mechanism was developed to wake up the SNTAP using a simple string of constant values (0 or 1) on the TMS input. Two new mechanisms to wake up SNTAP by means of an instruction scanned in, are described in this report. Both mechanisms allow embedded 1149.1-compliant TAP's to be used in a hierarchical design, as is, without any hardware modification. Moreover, both mechanisms enable reuse of the test program from the embedded TAP'ed cores, without any modification. The instructions to wake up the SNTAP - to switch access to different TAP-ed cores - can be simply inserted in-between the test programs for the embedded cores.