A Flexible Path Selection Procedure for Path Delay Fault Testing

V
VTS
1999
1999 17TH IEEE VLSI Test Symposium
Abstract - A Flexible Path Selection Procedure for Path Delay Fault Testing

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	Similar Articles Articles by Irith Pomeranz Articles by Sudhakar M. Reddy

1999 17TH IEEE VLSI Test Symposium

San Diego, California

April 26-April 30

ISBN: 0-7695-0146-X

	ASCII Text	x
	Irith Pomeranz, Sudhakar M. Reddy, "A Flexible Path Selection Procedure for Path Delay Fault Testing," VLSI Test Symposium, IEEE, pp. 152, 1999 17TH IEEE VLSI Test Symposium, 1999.

	BibTex	x
	@article{ 10.1109/VTEST.1999.766659, author = {Irith Pomeranz and Sudhakar M. Reddy}, title = {A Flexible Path Selection Procedure for Path Delay Fault Testing}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {1999}, issn = {1093-0167}, pages = {152}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.1999.766659}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Test Symposium, IEEE TI - A Flexible Path Selection Procedure for Path Delay Fault Testing SN - 1093-0167 SP EP A1 - Irith Pomeranz, A1 - Sudhakar M. Reddy, PY - 1999 VL - 0 JA - VLSI Test Symposium, IEEE ER -

Irith Pomeranz, University of Iowa

Sudhakar M. Reddy, University of Iowa

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTEST.1999.766659

We describe a path selection procedure that selects target faults for path delay fault test generation. Since large numbers of path delay faults may be untestable, the proposed procedure does not select a fixed set of paths. Instead, it provides compactly represented subsets of paths, referred to as superpaths, and allows the test generation procedure to select one path out of each subset based on testability considerations.

Citation:

Irith Pomeranz, Sudhakar M. Reddy, "A Flexible Path Selection Procedure for Path Delay Fault Testing," vts, pp.152, 1999 17TH IEEE VLSI Test Symposium, 1999

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