Using Temporal Constraints for Eliminating Crosstalk Candidates for Design and Test

V
VTS
1999
1999 17TH IEEE VLSI Test Symposium
Abstract - Using Temporal Constraints for Eliminating Crosstalk Candidates for Design and Test

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	Similar Articles Articles by Michael A. Margolese Articles by F. Joel Ferguson

1999 17TH IEEE VLSI Test Symposium

San Diego, California

April 26-April 30

ISBN: 0-7695-0146-X

	ASCII Text	x
	Michael A. Margolese, F. Joel Ferguson, "Using Temporal Constraints for Eliminating Crosstalk Candidates for Design and Test," VLSI Test Symposium, IEEE, pp. 80, 1999 17TH IEEE VLSI Test Symposium, 1999.

	BibTex	x
	@article{ 10.1109/VTEST.1999.766650, author = {Michael A. Margolese and F. Joel Ferguson}, title = {Using Temporal Constraints for Eliminating Crosstalk Candidates for Design and Test}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {1999}, issn = {1093-0167}, pages = {80}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.1999.766650}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Test Symposium, IEEE TI - Using Temporal Constraints for Eliminating Crosstalk Candidates for Design and Test SN - 1093-0167 SP EP A1 - Michael A. Margolese, A1 - F. Joel Ferguson, PY - 1999 VL - 0 JA - VLSI Test Symposium, IEEE ER -

Michael A. Margolese, University of California, at Santa Cruz

F. Joel Ferguson, University of California, at Santa Cruz

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTEST.1999.766650

This paper describes a simple algorithm for eliminating possible aggressor-victim net pairs for crosstalk analysis. This algorithm makes use of the observation that timing constraints in sequential circuits apply to crosstalk induced pulses. We show how this algorithm can be applied to a design to prune the candidate list for ATPG to detect crosstalk glitches that are introduced by manufacturing defects.

Citation:

Michael A. Margolese, F. Joel Ferguson, "Using Temporal Constraints for Eliminating Crosstalk Candidates for Design and Test," vts, pp.80, 1999 17TH IEEE VLSI Test Symposium, 1999

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