20.2 New Techniques for Deterministic Test Pattern Generation

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16th IEEE VLSI Test Symposium

Monterey, California

April 26-April 30

ISBN: 0-8186-8436-4

	ASCII Text	x
	I. Hamzaoglu, J.H. Patel, "20.2 New Techniques for Deterministic Test Pattern Generation," VLSI Test Symposium, IEEE, pp. 446, 16th IEEE VLSI Test Symposium, 1998.

	BibTex	x
	@article{ 10.1109/VTEST.1998.670910, author = {I. Hamzaoglu and J.H. Patel}, title = {20.2 New Techniques for Deterministic Test Pattern Generation}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {1998}, issn = {1093-0167}, pages = {446}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.1998.670910}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Test Symposium, IEEE TI - 20.2 New Techniques for Deterministic Test Pattern Generation SN - 1093-0167 SP EP A1 - I. Hamzaoglu, A1 - J.H. Patel, PY - 1998 VL - 0 JA - VLSI Test Symposium, IEEE ER -

Citation:

I. Hamzaoglu, J.H. Patel, "20.2 New Techniques for Deterministic Test Pattern Generation," vts, pp.446, 16th IEEE VLSI Test Symposium, 1998

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