10.1 Towards Simultaneous Delay-Fault Built-In Self-Test and Partial-Scan Insertion

V
VTS
1998
16th IEEE VLSI Test Symposium
Abstract - 10.1 Towards Simultaneous Delay-Fault Built-In Self-Test and Partial-Scan Insertion

	This Article
	Subscribers, please Login Purchase article: $19 PDF IEEE Xplore Subscribers RSS feed
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by G. Parthasarathy Articles by M.L. Bushnell

16th IEEE VLSI Test Symposium

Monterey, California

April 26-April 30

ISBN: 0-8186-8436-4

	ASCII Text	x
	G. Parthasarathy, M.L. Bushnell, "10.1 Towards Simultaneous Delay-Fault Built-In Self-Test and Partial-Scan Insertion," VLSI Test Symposium, IEEE, pp. 210, 16th IEEE VLSI Test Symposium, 1998.

	BibTex	x
	@article{ 10.1109/VTEST.1998.670870, author = {G. Parthasarathy and M.L. Bushnell}, title = {10.1 Towards Simultaneous Delay-Fault Built-In Self-Test and Partial-Scan Insertion}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {1998}, issn = {1093-0167}, pages = {210}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.1998.670870}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Test Symposium, IEEE TI - 10.1 Towards Simultaneous Delay-Fault Built-In Self-Test and Partial-Scan Insertion SN - 1093-0167 SP EP A1 - G. Parthasarathy, A1 - M.L. Bushnell, PY - 1998 VL - 0 JA - VLSI Test Symposium, IEEE ER -

G. Parthasarathy

M.L. Bushnell

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTEST.1998.670870

Citation:

G. Parthasarathy, M.L. Bushnell, "10.1 Towards Simultaneous Delay-Fault Built-In Self-Test and Partial-Scan Insertion," vts, pp.210, 16th IEEE VLSI Test Symposium, 1998

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.