9.3 Improving Path Delay Fault Testability by Path Removal

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16th IEEE VLSI Test Symposium

Monterey, California

April 26-April 30

ISBN: 0-8186-8436-4

	ASCII Text	x
	U. Sparmann, L. Köller, "9.3 Improving Path Delay Fault Testability by Path Removal," VLSI Test Symposium, IEEE, pp. 200, 16th IEEE VLSI Test Symposium, 1998.

	BibTex	x
	@article{ 10.1109/VTEST.1998.670869, author = {U. Sparmann and L. Köller}, title = {9.3 Improving Path Delay Fault Testability by Path Removal}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {1998}, issn = {1093-0167}, pages = {200}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.1998.670869}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Test Symposium, IEEE TI - 9.3 Improving Path Delay Fault Testability by Path Removal SN - 1093-0167 SP EP A1 - U. Sparmann, A1 - L. Köller, PY - 1998 VL - 0 JA - VLSI Test Symposium, IEEE ER -

Citation:

U. Sparmann, L. Köller, "9.3 Improving Path Delay Fault Testability by Path Removal," vts, pp.200, 16th IEEE VLSI Test Symposium, 1998

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