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16th IEEE VLSI Test Symposium
8.2 On Synchronizing Sequences and Test Sequence Partitioning
Monterey, California
April 26-April 30
ISBN: 0-8186-8436-4
ASCII Text
x 
 
I. Pomeranz, S.M. Reddy, "8.2 On Synchronizing Sequences and Test Sequence Partitioning," VLSI Test Symposium, IEEE, pp. 158, 16th IEEE VLSI Test Symposium, 1998.
 
 
BibTex
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@article{ 10.1109/VTEST.1998.670864,
author = {I. Pomeranz and S.M. Reddy},
title = {8.2 On Synchronizing Sequences and Test Sequence Partitioning},
journal ={VLSI Test Symposium, IEEE},
volume = {0},
year = {1998},
issn = {1093-0167},
pages = {158},
doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.1998.670864},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Test Symposium, IEEE
TI - 8.2 On Synchronizing Sequences and Test Sequence Partitioning
SN - 1093-0167
SP
EP
A1 - I. Pomeranz,
A1 - S.M. Reddy,
PY - 1998
VL - 0
JA - VLSI Test Symposium, IEEE
ER -
 
Citation:
I. Pomeranz, S.M. Reddy, "8.2 On Synchronizing Sequences and Test Sequence Partitioning," vts, pp.158, 16th IEEE VLSI Test Symposium, 1998
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