P.N. Variyam, A. Chatterjee, "7.2 Enhancing Test Effectiveness for Analog Circuits Using Synthesized Measurements," VLSI Test Symposium, IEEE, pp. 132, 16th IEEE VLSI Test Symposium, 1998.

@article{ 10.1109/VTEST.1998.670860,
author = {P.N. Variyam and A. Chatterjee},
title = {7.2 Enhancing Test Effectiveness for Analog Circuits Using Synthesized Measurements},
journal ={VLSI Test Symposium, IEEE},
volume = {0},
year = {1998},
issn = {1093-0167},
pages = {132},
doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.1998.670860},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}

TY - CONF
JO - VLSI Test Symposium, IEEE
TI - 7.2 Enhancing Test Effectiveness for Analog Circuits Using Synthesized Measurements
SN - 1093-0167
SP
EP
A1 - P.N. Variyam,
A1 - A. Chatterjee,
PY - 1998
VL - 0
JA - VLSI Test Symposium, IEEE
ER -