T.A. García, A.J. Acosta, J.L. Huertas, J.M. Mora, J. Ramos, "5.2 Self-Timed Boundary-Scan Cells for Multi-Chip Module Test," VLSI Test Symposium, IEEE, pp. 92, 16th IEEE VLSI Test Symposium, 1998.

@article{ 10.1109/VTEST.1998.670854,
author = {T.A. García and A.J. Acosta and J.L. Huertas and J.M. Mora and J. Ramos},
title = {5.2 Self-Timed Boundary-Scan Cells for Multi-Chip Module Test},
journal ={VLSI Test Symposium, IEEE},
volume = {0},
year = {1998},
issn = {1093-0167},
pages = {92},
doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.1998.670854},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}

TY - CONF
JO - VLSI Test Symposium, IEEE
TI - 5.2 Self-Timed Boundary-Scan Cells for Multi-Chip Module Test
SN - 1093-0167
SP
EP
A1 - T.A. García,
A1 - A.J. Acosta,
A1 - J.L. Huertas,
A1 - J.M. Mora,
A1 - J. Ramos,
PY - 1998
VL - 0
JA - VLSI Test Symposium, IEEE
ER -