A. Majumdar, M. Komoda, T. Ayres, "5.1 Ground Bounce Considerations in DC Parametric Test Generation Using Boundary Scan," VLSI Test Symposium, IEEE, pp. 86, 16th IEEE VLSI Test Symposium, 1998.

@article{ 10.1109/VTEST.1998.670853,
author = {A. Majumdar and M. Komoda and T. Ayres},
title = {5.1 Ground Bounce Considerations in DC Parametric Test Generation Using Boundary Scan},
journal ={VLSI Test Symposium, IEEE},
volume = {0},
year = {1998},
issn = {1093-0167},
pages = {86},
doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.1998.670853},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}

TY - CONF
JO - VLSI Test Symposium, IEEE
TI - 5.1 Ground Bounce Considerations in DC Parametric Test Generation Using Boundary Scan
SN - 1093-0167
SP
EP
A1 - A. Majumdar,
A1 - M. Komoda,
A1 - T. Ayres,
PY - 1998
VL - 0
JA - VLSI Test Symposium, IEEE
ER -