4.3 Bit Serial Pattern Generation and Response Compaction Using Arithmetic Functions

	This Article
	Subscribers, please Login Purchase article: $19 PDF IEEE Xplore Subscribers RSS feed
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by A.P. Stroele

16th IEEE VLSI Test Symposium

Monterey, California

April 26-April 30

ISBN: 0-8186-8436-4

	ASCII Text	x
	A.P. Stroele, "4.3 Bit Serial Pattern Generation and Response Compaction Using Arithmetic Functions," VLSI Test Symposium, IEEE, pp. 78, 16th IEEE VLSI Test Symposium, 1998.

	BibTex	x
	@article{ 10.1109/VTEST.1998.670852, author = {A.P. Stroele}, title = {4.3 Bit Serial Pattern Generation and Response Compaction Using Arithmetic Functions}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {1998}, issn = {1093-0167}, pages = {78}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.1998.670852}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Test Symposium, IEEE TI - 4.3 Bit Serial Pattern Generation and Response Compaction Using Arithmetic Functions SN - 1093-0167 SP EP A1 - A.P. Stroele, PY - 1998 VL - 0 JA - VLSI Test Symposium, IEEE ER -

Citation:

A.P. Stroele, "4.3 Bit Serial Pattern Generation and Response Compaction Using Arithmetic Functions," vts, pp.78, 16th IEEE VLSI Test Symposium, 1998

Usage of this product signifies your acceptance of the Terms of Use.