K. Shigeta, T. Ishiyama, "3.2 A New Path Tracing Algorithm with Dynamic Circuit Extraction for Sequential Circuit Fault Diagnosis," VLSI Test Symposium, IEEE, pp. 48, 16th IEEE VLSI Test Symposium, 1998.

@article{ 10.1109/VTEST.1998.670848,
author = {K. Shigeta and T. Ishiyama},
title = {3.2 A New Path Tracing Algorithm with Dynamic Circuit Extraction for Sequential Circuit Fault Diagnosis},
journal ={VLSI Test Symposium, IEEE},
volume = {0},
year = {1998},
issn = {1093-0167},
pages = {48},
doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.1998.670848},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}

TY - CONF
JO - VLSI Test Symposium, IEEE
TI - 3.2 A New Path Tracing Algorithm with Dynamic Circuit Extraction for Sequential Circuit Fault Diagnosis
SN - 1093-0167
SP
EP
A1 - K. Shigeta,
A1 - T. Ishiyama,
PY - 1998
VL - 0
JA - VLSI Test Symposium, IEEE
ER -