1.3 Parallelism in Structural Fault Testing of Embedded Cores

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16th IEEE VLSI Test Symposium

Monterey, California

April 26-April 30

ISBN: 0-8186-8436-4

	ASCII Text	x
	M. Nourani, C. Papachristou, "1.3 Parallelism in Structural Fault Testing of Embedded Cores," VLSI Test Symposium, IEEE, pp. 15, 16th IEEE VLSI Test Symposium, 1998.

	BibTex	x
	@article{ 10.1109/VTEST.1998.670843, author = {M. Nourani and C. Papachristou}, title = {1.3 Parallelism in Structural Fault Testing of Embedded Cores}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {1998}, issn = {1093-0167}, pages = {15}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.1998.670843}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Test Symposium, IEEE TI - 1.3 Parallelism in Structural Fault Testing of Embedded Cores SN - 1093-0167 SP EP A1 - M. Nourani, A1 - C. Papachristou, PY - 1998 VL - 0 JA - VLSI Test Symposium, IEEE ER -

Citation:

M. Nourani, C. Papachristou, "1.3 Parallelism in Structural Fault Testing of Embedded Cores," vts, pp.15, 16th IEEE VLSI Test Symposium, 1998

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