1.2 Hierarchical Test Access Architecture for Embedded Cores in an Integrated Circuit

V
VTS
1998
16th IEEE VLSI Test Symposium
Abstract - 1.2 Hierarchical Test Access Architecture for Embedded Cores in an Integrated Circuit

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16th IEEE VLSI Test Symposium

Monterey, California

April 26-April 30

ISBN: 0-8186-8436-4

	ASCII Text	x
	D. Bhattacharya, "1.2 Hierarchical Test Access Architecture for Embedded Cores in an Integrated Circuit," VLSI Test Symposium, IEEE, pp. 8, 16th IEEE VLSI Test Symposium, 1998.

	BibTex	x
	@article{ 10.1109/VTEST.1998.670842, author = {D. Bhattacharya}, title = {1.2 Hierarchical Test Access Architecture for Embedded Cores in an Integrated Circuit}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {1998}, issn = {1093-0167}, pages = {8}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.1998.670842}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Test Symposium, IEEE TI - 1.2 Hierarchical Test Access Architecture for Embedded Cores in an Integrated Circuit SN - 1093-0167 SP EP A1 - D. Bhattacharya, PY - 1998 VL - 0 JA - VLSI Test Symposium, IEEE ER -

D. Bhattacharya

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTEST.1998.670842

Citation:

D. Bhattacharya, "1.2 Hierarchical Test Access Architecture for Embedded Cores in an Integrated Circuit," vts, pp.8, 16th IEEE VLSI Test Symposium, 1998

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