Citation:
S.V. Kosonocky, A. Bright, K. Warren, R.A. Haring, S. Klepner, S. Asaad, S. Basavaiah, B. Havreluk, D. Heidel, M. Immediato, K. Jenkins, R. Joshi, B. Parker, T.V. Rajeevakumar, K. Stawiasz, "1.1 Designing a Testable System on a Chip," vts, pp.2, 16th IEEE VLSI Test Symposium, 1998