S.V. Kosonocky, A. Bright, K. Warren, R.A. Haring, S. Klepner, S. Asaad, S. Basavaiah, B. Havreluk, D. Heidel, M. Immediato, K. Jenkins, R. Joshi, B. Parker, T.V. Rajeevakumar, K. Stawiasz, "1.1 Designing a Testable System on a Chip," VLSI Test Symposium, IEEE, pp. 2, 16th IEEE VLSI Test Symposium, 1998.

@article{ 10.1109/VTEST.1998.670841,
author = {S.V. Kosonocky and A. Bright and K. Warren and R.A. Haring and S. Klepner and S. Asaad and S. Basavaiah and B. Havreluk and D. Heidel and M. Immediato and K. Jenkins and R. Joshi and B. Parker and T.V. Rajeevakumar and K. Stawiasz},
title = {1.1 Designing a Testable System on a Chip},
journal ={VLSI Test Symposium, IEEE},
volume = {0},
year = {1998},
issn = {1093-0167},
pages = {2},
doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.1998.670841},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}

TY - CONF
JO - VLSI Test Symposium, IEEE
TI - 1.1 Designing a Testable System on a Chip
SN - 1093-0167
SP
EP
A1 - S.V. Kosonocky,
A1 - A. Bright,
A1 - K. Warren,
A1 - R.A. Haring,
A1 - S. Klepner,
A1 - S. Asaad,
A1 - S. Basavaiah,
A1 - B. Havreluk,
A1 - D. Heidel,
A1 - M. Immediato,
A1 - K. Jenkins,
A1 - R. Joshi,
A1 - B. Parker,
A1 - T.V. Rajeevakumar,
A1 - K. Stawiasz,
PY - 1998
VL - 0
JA - VLSI Test Symposium, IEEE
ER -