Automated test pattern generation for analog integrated circuits

V
VTS
1997
15th IEEE VLSI Test Symposium (VTS'97)
Abstract - Automated test pattern generation for analog integrated circuits

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	Similar Articles Articles by W. Verhaegen Articles by G. Van der Plas Articles by G. Gielen

15th IEEE VLSI Test Symposium (VTS'97)

Monterey, California

April 27-May 01

ISBN: 0-8186-7810-0

	ASCII Text	x
	W. Verhaegen, G. Van der Plas, G. Gielen, "Automated test pattern generation for analog integrated circuits," VLSI Test Symposium, IEEE, pp. 296, 15th IEEE VLSI Test Symposium (VTS'97), 1997.

	BibTex	x
	@article{ 10.1109/VTEST.1997.600291, author = {W. Verhaegen and G. Van der Plas and G. Gielen}, title = {Automated test pattern generation for analog integrated circuits}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {1997}, isbn = {0-8186-7810-0}, pages = {296}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.1997.600291}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Test Symposium, IEEE TI - Automated test pattern generation for analog integrated circuits SN - 0-8186-7810-0 SP EP A1 - W. Verhaegen, A1 - G. Van der Plas, A1 - G. Gielen, PY - 1997 KW - analogue integrated circuits; automated test pattern generation; analog integrated circuits; generated fault list; optimal test signals; statistical fluctuations; statistical test criterion; ATPG algorithm VL - 0 JA - VLSI Test Symposium, IEEE ER -

W. Verhaegen, ESAT, Katholieke Univ., Leuven, Heverlee, Belgium

G. Van der Plas, ESAT, Katholieke Univ., Leuven, Heverlee, Belgium

G. Gielen, ESAT, Katholieke Univ., Leuven, Heverlee, Belgium

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTEST.1997.600291

An algorithm for the generation of tests for analog integrated circuits is proposed. It starts from a generated fault list and ranges specified by the user and determines optimal test signals that maximize the detectability of all faults. As statistical fluctuations have to be considered when evaluating analog circuits, it is based on a statistical test criterion. Two examples demonstrate the practical use and versatility of this approach.

Index Terms:

analogue integrated circuits; automated test pattern generation; analog integrated circuits; generated fault list; optimal test signals; statistical fluctuations; statistical test criterion; ATPG algorithm

Citation:

W. Verhaegen, G. Van der Plas, G. Gielen, "Automated test pattern generation for analog integrated circuits," vts, pp.296, 15th IEEE VLSI Test Symposium (VTS'97), 1997

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