Both simulation for design verification and fault simulation in conjunction with automatic test pattern generation (ATPG) would benefit from forward and backward shifting of the simulation time. Except in some particular cases, however, this has so far been only allowed through explicit save/restore commands issued by the user. The paper presents a general technique that makes a "run for T" command possible, where T can be any positive or negative time value. A major feature is that the user can set the maximum allowable overhead. Its generality allows its implementation in simulators for design verification and fault simulators, for both synchronous and asynchronous circuits, with either zero-delay or accurate delay models