Low-cost and efficient digital-compatible BIST for analog circuits using pulse response sampling

V
VTS
1997
15th IEEE VLSI Test Symposium (VTS'97)
Abstract - Low-cost and efficient digital-compatible BIST for analog circuits using pulse response sampling

	This Article
	Subscribers, please Login Purchase article: $19 PDF IEEE Xplore Subscribers RSS feed
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by P.N. Variyam Articles by A. Chatterjeee Articles by N. Nagi

15th IEEE VLSI Test Symposium (VTS'97)

Monterey, California

April 27-May 01

ISBN: 0-8186-7810-0

	ASCII Text	x
	P.N. Variyam, A. Chatterjeee, N. Nagi, "Low-cost and efficient digital-compatible BIST for analog circuits using pulse response sampling," VLSI Test Symposium, IEEE, pp. 261, 15th IEEE VLSI Test Symposium (VTS'97), 1997.

	BibTex	x
	@article{ 10.1109/VTEST.1997.600285, author = {P.N. Variyam and A. Chatterjeee and N. Nagi}, title = {Low-cost and efficient digital-compatible BIST for analog circuits using pulse response sampling}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {1997}, isbn = {0-8186-7810-0}, pages = {261}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.1997.600285}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Test Symposium, IEEE TI - Low-cost and efficient digital-compatible BIST for analog circuits using pulse response sampling SN - 0-8186-7810-0 SP EP A1 - P.N. Variyam, A1 - A. Chatterjeee, A1 - N. Nagi, PY - 1997 KW - built-in self test; digital-compatible BIST scheme; analog circuits; pulse response sampling; low-cost BIST scheme; built-in self test scheme; rectangular pulses; digital linear feedback shift register; transient testing; synchronization circuitry; comparison circuitry; BIST hardware design VL - 0 JA - VLSI Test Symposium, IEEE ER -

P.N. Variyam, Sch. of Electr. Eng., Georgia Inst. of Technol., Atlanta, GA, USA

A. Chatterjeee, Sch. of Electr. Eng., Georgia Inst. of Technol., Atlanta, GA, USA

N. Nagi, Sch. of Electr. Eng., Georgia Inst. of Technol., Atlanta, GA, USA

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTEST.1997.600285

In this paper an efficient low-cost built-in self test (BIST) scheme is proposed for analog circuits. The key idea is to use rectangular pulses of random widths obtained directly from a digital linear feedback shift register to perform transient testing of the circuit under test. A small amount of synchronization and comparison circuitry is necessary to perform the BIST. A methodology for designing the BIST hardware is described and results are discussed. The method is seen to be both efficient and low cost.

Index Terms:

built-in self test; digital-compatible BIST scheme; analog circuits; pulse response sampling; low-cost BIST scheme; built-in self test scheme; rectangular pulses; digital linear feedback shift register; transient testing; synchronization circuitry; comparison circuitry; BIST hardware design

Citation:

P.N. Variyam, A. Chatterjeee, N. Nagi, "Low-cost and efficient digital-compatible BIST for analog circuits using pulse response sampling," vts, pp.261, 15th IEEE VLSI Test Symposium (VTS'97), 1997

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.