Self-exercising self testing k-order comparators

V
VTS
1997
15th IEEE VLSI Test Symposium (VTS'97)
Abstract - Self-exercising self testing k-order comparators

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15th IEEE VLSI Test Symposium (VTS'97)

Monterey, California

April 27-May 01

ISBN: 0-8186-7810-0

	ASCII Text	x
	X. Kavousianos, D. Nikolos, "Self-exercising self testing k-order comparators," VLSI Test Symposium, IEEE, pp. 216, 15th IEEE VLSI Test Symposium (VTS'97), 1997.

	BibTex	x
	@article{ 10.1109/VTEST.1997.600275, author = {X. Kavousianos and D. Nikolos}, title = {Self-exercising self testing k-order comparators}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {1997}, isbn = {0-8186-7810-0}, pages = {216}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.1997.600275}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Test Symposium, IEEE TI - Self-exercising self testing k-order comparators SN - 0-8186-7810-0 SP EP A1 - X. Kavousianos, A1 - D. Nikolos, PY - 1997 KW - built-in self test; self testing k-order comparators; self-exercising comparators; combinational circuit; equality comparator; error correction codes; error detection codes; fault tolerant cache memory; broadcast networks VL - 0 JA - VLSI Test Symposium, IEEE ER -

X. Kavousianos, Dept. of Comput. Eng. & Inf., Patras Univ., Greece

D. Nikolos, Dept. of Comput. Eng. & Inf., Patras Univ., Greece

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTEST.1997.600275

In this paper we give a systematic method to design self-exercising (SE) self testing k-order comparators. The k-order comparator is defined as a combinational circuit that compares two operands and decides if these differ in less than k bits. According to this definition the usual equality comparator is the 1st-order comparator. Also in this paper we discuss the applicability of the k-order comparators in the implementation of (k-1)-EC/AUED, (k-1)-EC/d-ED/AUED, (k-1)-EC/d-UED and (k-1)-EC/d-ED/f-UED codes as well as in the design of a fault tolerant cache memory and broadcast networks.

Index Terms:

built-in self test; self testing k-order comparators; self-exercising comparators; combinational circuit; equality comparator; error correction codes; error detection codes; fault tolerant cache memory; broadcast networks

Citation:

X. Kavousianos, D. Nikolos, "Self-exercising self testing k-order comparators," vts, pp.216, 15th IEEE VLSI Test Symposium (VTS'97), 1997

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