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15th IEEE VLSI Test Symposium (VTS'97)
Extension of Inductive Fault Analysis to Parametric Faults in Analog Circuits with Application to Test Generation
Monterey, California
April 27-May 01
ISBN: 0-8186-7810-0
ASCII Text
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Zbigniew Jaworski, Mariusz Niewczas, Wieslaw Kuzmicz, "Extension of Inductive Fault Analysis to Parametric Faults in Analog Circuits with Application to Test Generation," VLSI Test Symposium, IEEE, pp. 172, 15th IEEE VLSI Test Symposium (VTS'97), 1997.
 
 
BibTex
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@article{ 10.1109/VTEST.1997.600249,
author = {Zbigniew Jaworski and Mariusz Niewczas and Wieslaw Kuzmicz},
title = {Extension of Inductive Fault Analysis to Parametric Faults in Analog Circuits with Application to Test Generation},
journal ={VLSI Test Symposium, IEEE},
volume = {0},
year = {1997},
isbn = {0-8186-7810-0},
pages = {172},
doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.1997.600249},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Test Symposium, IEEE
TI - Extension of Inductive Fault Analysis to Parametric Faults in Analog Circuits with Application to Test Generation
SN - 0-8186-7810-0
SP
EP
A1 - Zbigniew Jaworski,
A1 - Mariusz Niewczas,
A1 - Wieslaw Kuzmicz,
PY - 1997
VL - 0
JA - VLSI Test Symposium, IEEE
ER -
 
Zbigniew Jaworski, Institute of Microelectronics and Optoelectronics Warsaw University of Technology zj@imio.pw.edu.pl, mn@imio.pw.edu.pl, wbk@imio.pw.edu.pl
Mariusz Niewczas, Institute of Microelectronics and Optoelectronics Warsaw University of Technology zj@imio.pw.edu.pl, mn@imio.pw.edu.pl, wbk@imio.pw.edu.pl
Wieslaw Kuzmicz, Institute of Microelectronics and Optoelectronics Warsaw University of Technology zj@imio.pw.edu.pl, mn@imio.pw.edu.pl, wbk@imio.pw.edu.pl
Parametric fault modeling methodology based on statistical process simulation is proposed. Statistical simulation based on process disturbances allows to avoid testing for faults which are unlikely to occur. As a result, the number of tests required to verify the circuit's performance is reduced. A practical example with results measured on prototype chips is presented.
Citation:
Zbigniew Jaworski, Mariusz Niewczas, Wieslaw Kuzmicz, "Extension of Inductive Fault Analysis to Parametric Faults in Analog Circuits with Application to Test Generation," vts, pp.172, 15th IEEE VLSI Test Symposium (VTS'97), 1997
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