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15th IEEE VLSI Test Symposium (VTS'97)
Using fault sampling to compute I/sub DDQ/ diagnostic test sets
Monterey, California
April 27-May 01
ISBN: 0-8186-7810-0
Yiming Gong, Quickturn Syst. Inc., Mountain View, CA, USA
S. Chakravarty, Quickturn Syst. Inc., Mountain View, CA, USA
A diagnostic test generation system for computing I/sub DQQ/ diagnostic test sets for bridging faults in combinational circuits is presented. The system uses fault sampling. Experimental results presented show that fault sampling is a very effective method for computing diagnostic test sets, especially when the number of target faults is very large.
Index Terms:
combinational circuits; fault sampling; IDDQ diagnostic test set generation; bridging faults; combinational circuit
Citation:
Yiming Gong, S. Chakravarty, "Using fault sampling to compute I/sub DDQ/ diagnostic test sets," vts, pp.74, 15th IEEE VLSI Test Symposium (VTS'97), 1997
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