15th IEEE VLSI Test Symposium (VTS'97) Using fault sampling to compute I/sub DDQ/ diagnostic test sets Monterey, California April 27-May 01 ISBN: 0-8186-7810-0
A diagnostic test generation system for computing I/sub DQQ/ diagnostic test sets for bridging faults in combinational circuits is presented. The system uses fault sampling. Experimental results presented show that fault sampling is a very effective method for computing diagnostic test sets, especially when the number of target faults is very large.
Index Terms:
combinational circuits; fault sampling; IDDQ diagnostic test set generation; bridging faults; combinational circuit
Citation:
Yiming Gong, S. Chakravarty, "Using fault sampling to compute I/sub DDQ/ diagnostic test sets," vts, pp.74, 15th IEEE VLSI Test Symposium (VTS'97), 1997 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||