15th IEEE VLSI Test Symposium (VTS'97)
Implicit test pattern generation constrained to cellular automata embedding
Monterey, California
April 27-May 01
ISBN: 0-8186-7810-0
This paper presents an implicit methodology that constrains a test pattern generator to identify test sequences which can be reproduced by cellular automata (CA). The so identified CA can be synthesized as an autonomous finite state machine and can be attached to the inputs of a circuit under test (e.g., a controller). In this way, the circuit under test preserves its integrity and its performance is not affected by the proposed testing technique. The overall device (controller+CA) is an off-line self-testable circuit which con potentially self-test all stuck-at faults both of the controller and the CA. Thus, the method can be viewed as a BIST strategy based on the embedding of deterministic test sequences.
Index Terms:
built-in self test; implicit test pattern generation; cellular automata embedding; test sequence identification; autonomous finite state machine; circuit under test; controller; off-line self-testable circuit; stuck-at faults; BIST strategy; deterministic test sequences; ASIC design; MCNC benchmarks
Citation:
F. Fummi, D. Sciuto, "Implicit test pattern generation constrained to cellular automata embedding," vts, pp.54, 15th IEEE VLSI Test Symposium (VTS'97), 1997