Standard and ROM-based synthesis of FSMs with control flow checking capabilities

V
VTS
1996
14th IEEE VLSI Test Symposium (VTS '96)
Abstract - Standard and ROM-based synthesis of FSMs with control flow checking capabilities

	This Article
	Subscribers, please Login Purchase article: $19 PDF IEEE Xplore Subscribers RSS feed
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by X. Wendling Articles by R. Rochet Articles by R. Leveugle

14th IEEE VLSI Test Symposium (VTS '96)

Princeton, NJ

April 28-May 01

ISBN: 0-8186-7304-4

	ASCII Text	x
	X. Wendling, R. Rochet, R. Leveugle, "Standard and ROM-based synthesis of FSMs with control flow checking capabilities," VLSI Test Symposium, IEEE, pp. 81, 14th IEEE VLSI Test Symposium (VTS '96), 1996.

	BibTex	x
	@article{ 10.1109/VTEST.1996.510839, author = {X. Wendling and R. Rochet and R. Leveugle}, title = {Standard and ROM-based synthesis of FSMs with control flow checking capabilities}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {1996}, isbn = {0-8186-7304-4}, pages = {81}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.1996.510839}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Test Symposium, IEEE TI - Standard and ROM-based synthesis of FSMs with control flow checking capabilities SN - 0-8186-7304-4 SP EP A1 - X. Wendling, A1 - R. Rochet, A1 - R. Leveugle, PY - 1996 KW - finite state machines; integrated circuit design; integrated circuit testing; read-only storage; error detection; automatic testing; FSM; control flow checking; sequencing error detection; finite state machine; automatic synthesis; ROM architecture VL - 0 JA - VLSI Test Symposium, IEEE ER -

X. Wendling, Inst. Nat. Polytech. de Grenoble, France

R. Rochet, Inst. Nat. Polytech. de Grenoble, France

R. Leveugle, Inst. Nat. Polytech. de Grenoble, France

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTEST.1996.510839

This paper deals with the detection of sequencing errors in finite state machines. Several control-flow checking methods, implemented in an automatic synthesis tool, are presented. The contribution of this paper lies in that these methods are introduced in the ROM-based architecture, and compared to equivalent methods available in the standard synthesis flow.

Index Terms:

finite state machines; integrated circuit design; integrated circuit testing; read-only storage; error detection; automatic testing; FSM; control flow checking; sequencing error detection; finite state machine; automatic synthesis; ROM architecture

Citation:

X. Wendling, R. Rochet, R. Leveugle, "Standard and ROM-based synthesis of FSMs with control flow checking capabilities," vts, pp.81, 14th IEEE VLSI Test Symposium (VTS '96), 1996

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.