The multi-configuration: A DFT technique for analog circuits

V
VTS
1996
14th IEEE VLSI Test Symposium (VTS '96)
Abstract - The multi-configuration: A DFT technique for analog circuits

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	Similar Articles Articles by M. Renovell Articles by F. Azais Articles by Y. Bertrand

14th IEEE VLSI Test Symposium (VTS '96)

Princeton, NJ

April 28-May 01

ISBN: 0-8186-7304-4

	ASCII Text	x
	M. Renovell, F. Azais, Y. Bertrand, "The multi-configuration: A DFT technique for analog circuits," VLSI Test Symposium, IEEE, pp. 54, 14th IEEE VLSI Test Symposium (VTS '96), 1996.

	BibTex	x
	@article{ 10.1109/VTEST.1996.510835, author = {M. Renovell and F. Azais and Y. Bertrand}, title = {The multi-configuration: A DFT technique for analog circuits}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {1996}, isbn = {0-8186-7304-4}, pages = {54}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.1996.510835}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Test Symposium, IEEE TI - The multi-configuration: A DFT technique for analog circuits SN - 0-8186-7304-4 SP EP A1 - M. Renovell, A1 - F. Azais, A1 - Y. Bertrand, PY - 1996 KW - analogue integrated circuits; integrated circuit testing; design for testability; integrated circuit design; band-pass filters; DFT technique; analog circuits; multi-configuration technique; diagnosis facilities; 8/sup th/ order band pass filter VL - 0 JA - VLSI Test Symposium, IEEE ER -

M. Renovell, Lab. d'Inf., Robotique et Microelectronique, Montpellier, France

F. Azais, Lab. d'Inf., Robotique et Microelectronique, Montpellier, France

Y. Bertrand, Lab. d'Inf., Robotique et Microelectronique, Montpellier, France

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTEST.1996.510835

A Design-For-Testability (DFT) technique for analog circuits, called the Multi-Configuration technique is presented. This technique exhibits some flexibility features since different solutions are possible for its implementation. Different degrees of granularity are associated to the different solutions, corresponding to a given trade-off between implementation cost and test and/or diagnosis facilities. The multi-configuration technique is illustrated and validated on a 8/sup th/ order band pass filter.

Index Terms:

analogue integrated circuits; integrated circuit testing; design for testability; integrated circuit design; band-pass filters; DFT technique; analog circuits; multi-configuration technique; diagnosis facilities; 8/sup th/ order band pass filter

Citation:

M. Renovell, F. Azais, Y. Bertrand, "The multi-configuration: A DFT technique for analog circuits," vts, pp.54, 14th IEEE VLSI Test Symposium (VTS '96), 1996

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