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14th IEEE VLSI Test Symposium (VTS '96)
Optimization of analog IC test structures
Princeton, NJ
April 28-May 01
ISBN: 0-8186-7304-4
E. Felt, Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
A. Sangiovanni-Vincentelli, Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
A methodology for designing optimal analog integrated circuit test structures is presented. An optimal test structure is a circuit which allows one to characterize a specified set of circuit parameters as accurately as possible in the presence of measurement noise and other potential errors. The methodology is based upon recently developed statistical techniques for optimal design of experiments; these techniques allow analog systems to be characterized as accurately and efficiently as possible, thereby reducing cost and/or increasing accuracy. The usefulness of the methodology is illustrated with a fabricated circuit. The most interesting result is that relatively complex circuits are frequently more efficient than commonly used simple circuits.
Index Terms:
analogue integrated circuits; integrated circuit testing; integrated circuit measurement; integrated circuit noise; network parameters; design of experiments; statistical analysis; circuit optimisation; analog IC test structures; circuit parameters; measurement noise; statistical techniques; design of experiments; accuracy
Citation:
E. Felt, A. Sangiovanni-Vincentelli, "Optimization of analog IC test structures," vts, pp.48, 14th IEEE VLSI Test Symposium (VTS '96), 1996
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