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14th IEEE VLSI Test Symposium (VTS '96)
Segment delay faults: a new fault model
Princeton, NJ
April 28-May 01
ISBN: 0-8186-7304-4
K. Heragu, Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
J.H. Patel, Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
V.D. Agrawal, Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
We propose a segment delay fault model to represent any general delay defect ranging from a spot defect to a distributed defect. The segment length, L, is a parameter that can be chosen based on available statistics about the types of manufacturing defects. Once L is chosen, the fault list contains all segments of length L and paths whose entire lengths are less than L. Both rising and falling transitions at the origin of segments are considered. Choosing segments of a small length can prevent an explosion of the number of faults considered. At the same time, a defect over a segment may be large enough to affect any path passing through it. We present an efficient algorithm to compute the number of segments of any possible length in a circuit. We define various classes of segment delay fault tests-robust, transition, and non-robust-that offer a trade-off between fault coverage and quality.
Index Terms:
fault diagnosis; logic testing; delays; integrated circuit modelling; VLSI; integrated circuit testing; production testing; circuit analysis computing; automatic testing; segment delay faults; fault model; delay defect; spot defect; distributed defect; manufacturing defects; rising transitions; falling transitions; robust tests; transition tests; nonrobust tests
Citation:
K. Heragu, J.H. Patel, V.D. Agrawal, "Segment delay faults: a new fault model," vts, pp.32, 14th IEEE VLSI Test Symposium (VTS '96), 1996
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