A self-driven test structure for pseudorandom testing of non-scan sequential circuits

	This Article
	Subscribers, please Login Purchase article: $19 PDF IEEE Xplore Subscribers RSS feed
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan/Endnote
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by F. Muradali Articles by J. Rajski

14th IEEE VLSI Test Symposium (VTS '96)

Princeton, NJ

April 28-May 01

ISBN: 0-8186-7304-4

	ASCII Text	x
	F. Muradali, J. Rajski, "A self-driven test structure for pseudorandom testing of non-scan sequential circuits," VLSI Test Symposium, IEEE, pp. 17, 14th IEEE VLSI Test Symposium (VTS '96), 1996.

	BibTex	x
	@article{ 10.1109/VTEST.1996.510830, author = {F. Muradali and J. Rajski}, title = {A self-driven test structure for pseudorandom testing of non-scan sequential circuits}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {1996}, isbn = {0-8186-7304-4}, pages = {17}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.1996.510830}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Test Symposium, IEEE TI - A self-driven test structure for pseudorandom testing of non-scan sequential circuits SN - 0-8186-7304-4 SP EP A1 - F. Muradali, A1 - J. Rajski, PY - 1996 KW - built-in self test; integrated circuit testing; logic testing; sequential circuits; automatic testing; design for testability; self-driven test structure; primary inputs; nonscan sequential circuits; test point structure; parallel pseudorandom test patterns; circuit under test; test mode flag; stuck-at fault coverage; ISCAS-89 benchmarks; BIST VL - 0 JA - VLSI Test Symposium, IEEE ER -

F. Muradali, Dept. of Electr. Eng., McGill Univ., Montreal, Que., Canada

J. Rajski, Dept. of Electr. Eng., McGill Univ., Montreal, Que., Canada

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTEST.1996.510830

Introduced is a self-driven test point structure which permits at-speed, on-chip, non-scan, sequential testing using parallel pseudorandom test patterns applied only to the primary inputs of the circuit under test. The test network is unique in that aside from a test mode flag, all I/O signals needed for test system operation are tapped from within the circuit itself. High single stuck-at fault coverage is achieved for a number of ISCAS-89 benchmarks.

Index Terms:

built-in self test; integrated circuit testing; logic testing; sequential circuits; automatic testing; design for testability; self-driven test structure; primary inputs; nonscan sequential circuits; test point structure; parallel pseudorandom test patterns; circuit under test; test mode flag; stuck-at fault coverage; ISCAS-89 benchmarks; BIST

Citation:

F. Muradali, J. Rajski, "A self-driven test structure for pseudorandom testing of non-scan sequential circuits," vts, pp.17, 14th IEEE VLSI Test Symposium (VTS '96), 1996

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.