Test point insertion based on path tracing

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	Similar Articles Articles by N.A. Touba Articles by E.J. McCluskey

14th IEEE VLSI Test Symposium (VTS '96)

Princeton, NJ

April 28-May 01

ISBN: 0-8186-7304-4

	ASCII Text	x
	N.A. Touba, E.J. McCluskey, "Test point insertion based on path tracing," VLSI Test Symposium, IEEE, pp. 2, 14th IEEE VLSI Test Symposium (VTS '96), 1996.

	BibTex	x
	@article{ 10.1109/VTEST.1996.510828, author = {N.A. Touba and E.J. McCluskey}, title = {Test point insertion based on path tracing}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {1996}, isbn = {0-8186-7304-4}, pages = {2}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.1996.510828}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Test Symposium, IEEE TI - Test point insertion based on path tracing SN - 0-8186-7304-4 SP EP A1 - N.A. Touba, A1 - E.J. McCluskey, PY - 1996 KW - VLSI; fault diagnosis; logic testing; integrated circuit testing; probability; built-in self test; timing; automatic testing; test point insertion; path tracing; circuit-under-test; fault coverage; probabilistic techniques; primary inputs; insertion methods; BIST; logic testing; VLSI VL - 0 JA - VLSI Test Symposium, IEEE ER -

N.A. Touba, Center for Reliable Comput., Stanford Univ., CA, USA

E.J. McCluskey, Center for Reliable Comput., Stanford Univ., CA, USA

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTEST.1996.510828

This paper presents an innovative method for inserting test points in the circuit-under-test to obtain complete fault coverage for a specified set of test patterns. Rather than using probabilistic techniques for test point placement, a path tracing procedure is used to place both control and observation points. Rather than adding extra scan elements to drive the control points, a few of the existing primary inputs to the circuit are ANDed together to form signals that drive the control points. By selecting which patterns the control point is activated for, the effectiveness of each control point is maximized. A comparison is made with the best previously published results for other test point insertion methods, and it is shown that the proposed method requires fewer test points and less overhead to achieve the same or better fault coverage.

Index Terms:

VLSI; fault diagnosis; logic testing; integrated circuit testing; probability; built-in self test; timing; automatic testing; test point insertion; path tracing; circuit-under-test; fault coverage; probabilistic techniques; primary inputs; insertion methods; BIST; logic testing; VLSI

Citation:

N.A. Touba, E.J. McCluskey, "Test point insertion based on path tracing," vts, pp.2, 14th IEEE VLSI Test Symposium (VTS '96), 1996

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