Test pattern generation for I/sub DDQ/: increasing test quality

V
VTS
1995
13th IEEE VLSI Test Symposium (VTS'95)
Abstract - Test pattern generation for I/sub DDQ/: increasing test quality

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13th IEEE VLSI Test Symposium (VTS'95)

Princeton, New Jersey

April 30-May 03

ISBN: 0-8186-7000-2

	ASCII Text	x
	M. Dalpasso, M. Favalli, P. Olivo, "Test pattern generation for I/sub DDQ/: increasing test quality," VLSI Test Symposium, IEEE, pp. 0304, 13th IEEE VLSI Test Symposium (VTS'95), 1995.

	BibTex	x
	@article{ 10.1109/VTEST.1995.512653, author = {M. Dalpasso and M. Favalli and P. Olivo}, title = {Test pattern generation for I/sub DDQ/: increasing test quality}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {1995}, isbn = {0-8186-7000-2}, pages = {0304}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.1995.512653}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Test Symposium, IEEE TI - Test pattern generation for I/sub DDQ/: increasing test quality SN - 0-8186-7000-2 SP EP A1 - M. Dalpasso, A1 - M. Favalli, A1 - P. Olivo, PY - 1995 KW - automatic testing; integrated circuit testing; logic testing; CMOS logic circuits; test pattern generation; I/sub DDQ/ testing; ATPG strategy; fault coverage; quiescent power supply current monitoring VL - 0 JA - VLSI Test Symposium, IEEE ER -

M. Dalpasso, Dipartimento di Elettronica Inf. e Sistemistica, Bologna Univ., Italy

M. Favalli, Dipartimento di Elettronica Inf. e Sistemistica, Bologna Univ., Italy

P. Olivo, Dipartimento di Elettronica Inf. e Sistemistica, Bologna Univ., Italy

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTEST.1995.512653

Abstract: So far, the test pattern generation for I/sub DDQ/ testing has been performed without considering the value of the faulty current in comparison with the minimum current that is detectable as a fault: this approach will be shown to be misleading, since it actually gives optimistic coverage evaluation. Then, this work presents an ATPG strategy that targets the highest valves of current during the fault activation, in such a way that either a higher fault coverage can be obtained or a less accurate sensor can be used.

Index Terms:

automatic testing; integrated circuit testing; logic testing; CMOS logic circuits; test pattern generation; I/sub DDQ/ testing; ATPG strategy; fault coverage; quiescent power supply current monitoring

Citation:

M. Dalpasso, M. Favalli, P. Olivo, "Test pattern generation for I/sub DDQ/: increasing test quality," vts, pp.0304, 13th IEEE VLSI Test Symposium (VTS'95), 1995

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