High level fault modeling of asynchronous circuits

V
VTS
1995
13th IEEE VLSI Test Symposium (VTS'95)
Abstract - High level fault modeling of asynchronous circuits

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13th IEEE VLSI Test Symposium (VTS'95)

Princeton, New Jersey

April 30-May 03

ISBN: 0-8186-7000-2

	ASCII Text	x
	Ding Lu, C.Q. Tong, "High level fault modeling of asynchronous circuits," VLSI Test Symposium, IEEE, pp. 0190, 13th IEEE VLSI Test Symposium (VTS'95), 1995.

	BibTex	x
	@article{ 10.1109/VTEST.1995.512636, author = {Ding Lu and C.Q. Tong}, title = {High level fault modeling of asynchronous circuits}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {1995}, isbn = {0-8186-7000-2}, pages = {0190}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.1995.512636}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Test Symposium, IEEE TI - High level fault modeling of asynchronous circuits SN - 0-8186-7000-2 SP EP A1 - Ding Lu, A1 - C.Q. Tong, PY - 1995 KW - asynchronous circuits; fault diagnosis; logic testing; signal flow graphs; timing; high level fault modeling; asynchronous circuits; signal transition graph; transitional fault models; self-timed circuits; stuck-at-false model; stuck-at-true model VL - 0 JA - VLSI Test Symposium, IEEE ER -

Ding Lu, Dept. of Electr. Eng., Colorado State Univ., Fort Collins, CO, USA

C.Q. Tong, Dept. of Electr. Eng., Colorado State Univ., Fort Collins, CO, USA

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTEST.1995.512636

Abstract: A method is proposed for high level fault modeling of asynchronous circuits which are described by the signal transition graph. Transitional fault models are introduced. It is shown that the transitional faults are the direct mappings of most of the low level faults.

Index Terms:

asynchronous circuits; fault diagnosis; logic testing; signal flow graphs; timing; high level fault modeling; asynchronous circuits; signal transition graph; transitional fault models; self-timed circuits; stuck-at-false model; stuck-at-true model

Citation:

Ding Lu, C.Q. Tong, "High level fault modeling of asynchronous circuits," vts, pp.0190, 13th IEEE VLSI Test Symposium (VTS'95), 1995

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