13th IEEE VLSI Test Symposium (VTS'95) RT level testability-driven partitioning Princeton, New Jersey April 30-May 03 ISBN: 0-8186-7000-2
Abstract: This paper presents a method of partitioning RT level designs based on testability analysis results. The partitioning is carried out in two steps: (1) the data path of a design is partitioned at some hard-to-test points detected by the testability analysis algorithm. These points are made directly accessible by some DFT techniques; and (2) the control part of a design is modified to operate in two modes. In normal mode, the design is controlled to fulfill the design function. In test mode, each partition is controlled independently. As a result, ATPG and test application for each partition can be done independently. In this approach, each partition is guaranteed to be acyclic, have good testability measurements and suitable size and depth for the ATPG tool to be used. When BIST technique is used, it also guarantees that these partitions are not random pattern resistant. Experiment with four benchmarks has shown the improvements on fault coverage, ATPG time and test application time after partitioning.
Index Terms:
design for testability; logic partitioning; automatic testing; integrated circuit testing; logic CAD; fault diagnosis; logic testing; built-in self test; testability-driven partitioning; RT level designs; data path; hard-to-test points; testability analysis algorithm; DFT techniques; normal mode; design function; test mode; ATPG; acyclic partition; testability measurements; BIST technique; fault coverage; test application time
Citation:
Xinli Gu, "RT level testability-driven partitioning," vts, pp.0176, 13th IEEE VLSI Test Symposium (VTS'95), 1995 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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