Testability metrics for synthesis of self-testable designs and effective test plans

V
VTS
1995
13th IEEE VLSI Test Symposium (VTS'95)
Abstract - Testability metrics for synthesis of self-testable designs and effective test plans

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13th IEEE VLSI Test Symposium (VTS'95)

Princeton, New Jersey

April 30-May 03

ISBN: 0-8186-7000-2

	ASCII Text	x
	K. Vahidi, A. Orailoglu, "Testability metrics for synthesis of self-testable designs and effective test plans," VLSI Test Symposium, IEEE, pp. 0170, 13th IEEE VLSI Test Symposium (VTS'95), 1995.

	BibTex	x
	@article{ 10.1109/VTEST.1995.512633, author = {K. Vahidi and A. Orailoglu}, title = {Testability metrics for synthesis of self-testable designs and effective test plans}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {1995}, isbn = {0-8186-7000-2}, pages = {0170}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.1995.512633}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Test Symposium, IEEE TI - Testability metrics for synthesis of self-testable designs and effective test plans SN - 0-8186-7000-2 SP EP A1 - K. Vahidi, A1 - A. Orailoglu, PY - 1995 KW - high level synthesis; logic CAD; design for testability; built-in self test; VLSI; integrated circuit design; testability metrics; self-testable designs; effective test plans; unified metrics; synthesis phases; benchmark designs; VLSI; BIST; DFT; high level synthesis VL - 0 JA - VLSI Test Symposium, IEEE ER -

K. Vahidi, Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA

A. Orailoglu, Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTEST.1995.512633

Abstract: We propose a set of unified metrics for self-testability which are portable across different phases of synthesis. Furthermore, applicability of the proposed test metrics is verified through extensive experiments on benchmark designs.

Index Terms:

high level synthesis; logic CAD; design for testability; built-in self test; VLSI; integrated circuit design; testability metrics; self-testable designs; effective test plans; unified metrics; synthesis phases; benchmark designs; VLSI; BIST; DFT; high level synthesis

Citation:

K. Vahidi, A. Orailoglu, "Testability metrics for synthesis of self-testable designs and effective test plans," vts, pp.0170, 13th IEEE VLSI Test Symposium (VTS'95), 1995

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