Abstract: This paper will define and describe a methodology for testing wide buses in real-time at speed. In today's environment, computer buses are growing along with system clock speeds. These wide high-speed buses require special attention at time of board layout and analysis. Characterization of tests on a bus at high-speed cause unnecessary problems of tester interference. For example, the addition of capacitance by a logic analyzer is detrimental to the circuit performance. We have developed a technique to allow full-fault testing of these wide buses at multiple speeds, in real-time, without tester interference, using pseudo-random pattern generation, and allowing multiple seed and characteristic equations. This technique of testing the bus in a real-life environment allows the test engineer to evaluate the design in various operating environments with little or no undue influence on the design. We accomplish this by using the IEEE JTAG protocol to control and access the test logic.