Arithmetic built-in self test for high-level synthesis

V
VTS
1995
13th IEEE VLSI Test Symposium (VTS'95)
Abstract - Arithmetic built-in self test for high-level synthesis

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13th IEEE VLSI Test Symposium (VTS'95)

Princeton, New Jersey

April 30-May 03

ISBN: 0-8186-7000-2

	ASCII Text	x
	N. Mukherjee, H. Kassab, J. Rajski, J. Tyszer, "Arithmetic built-in self test for high-level synthesis," VLSI Test Symposium, IEEE, pp. 0132, 13th IEEE VLSI Test Symposium (VTS'95), 1995.

	BibTex	x
	@article{ 10.1109/VTEST.1995.512628, author = {N. Mukherjee and H. Kassab and J. Rajski and J. Tyszer}, title = {Arithmetic built-in self test for high-level synthesis}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {1995}, isbn = {0-8186-7000-2}, pages = {0132}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.1995.512628}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Test Symposium, IEEE TI - Arithmetic built-in self test for high-level synthesis SN - 0-8186-7000-2 SP EP A1 - N. Mukherjee, A1 - H. Kassab, A1 - J. Rajski, A1 - J. Tyszer, PY - 1995 KW - built-in self test; high level synthesis; logic CAD; logic testing; integrated circuit testing; arithmetic built-in self test; high-level synthesis; data path architectures; arithmetic blocks; test vectors; compact test responses; state coverage; testability; abstract level; testable circuit synthesis VL - 0 JA - VLSI Test Symposium, IEEE ER -

N. Mukherjee, Microelectron. & Comput. Syst. Lab., McGill Univ., Montreal, Que., Canada

H. Kassab, Microelectron. & Comput. Syst. Lab., McGill Univ., Montreal, Que., Canada

J. Rajski, Microelectron. & Comput. Syst. Lab., McGill Univ., Montreal, Que., Canada

J. Tyszer, Microelectron. & Comput. Syst. Lab., McGill Univ., Montreal, Que., Canada

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTEST.1995.512628

Abstract: In this paper, we propose an entirely new Built-in Self Test scheme for high-level synthesis of data path architectures that makes use of the arithmetic blocks in the data path to generate test vectors and compact test responses. The paper employs state coverage to evaluate testability in an abstract level, and subsequently, use it to guide the synthesis of testable circuits.

Index Terms:

built-in self test; high level synthesis; logic CAD; logic testing; integrated circuit testing; arithmetic built-in self test; high-level synthesis; data path architectures; arithmetic blocks; test vectors; compact test responses; state coverage; testability; abstract level; testable circuit synthesis

Citation:

N. Mukherjee, H. Kassab, J. Rajski, J. Tyszer, "Arithmetic built-in self test for high-level synthesis," vts, pp.0132, 13th IEEE VLSI Test Symposium (VTS'95), 1995

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