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13th IEEE VLSI Test Symposium (VTS'95)
The use of IDDQ testing in low stuck-at coverage situations
Princeton, New Jersey
April 30-May 03
ISBN: 0-8186-7000-2
ASCII Text
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P.C. Maxwell, "The use of IDDQ testing in low stuck-at coverage situations," VLSI Test Symposium, IEEE, pp. 0084, 13th IEEE VLSI Test Symposium (VTS'95), 1995.
 
 
BibTex
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@article{ 10.1109/VTEST.1995.512621,
author = {P.C. Maxwell},
title = {The use of IDDQ testing in low stuck-at coverage situations},
journal ={VLSI Test Symposium, IEEE},
volume = {0},
year = {1995},
isbn = {0-8186-7000-2},
pages = {0084},
doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.1995.512621},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Test Symposium, IEEE
TI - The use of IDDQ testing in low stuck-at coverage situations
SN - 0-8186-7000-2
SP
EP
A1 - P.C. Maxwell,
PY - 1995
KW - application specific integrated circuits; fault diagnosis; logic testing; integrated circuit testing; CMOS logic circuits; automatic testing; IDDQ testing; stuck-at coverage situations; IC testing; quality goal; graded coverage; composite metric; logic tests; ASIC
VL - 0
JA - VLSI Test Symposium, IEEE
ER -
 
P.C. Maxwell, Hewlett-Packard Co., USA
Abstract: An unresolved issue in IC testing is what mix of coverages of different types of test is required in order to achieve a given quality goal. This paper investigates the interaction between IDDQ and stuck-at coverage and examines the use of IDDQ to increase effective stuck-at coverage, particularly in situations where the graded coverage is lower than the desired goal. Empirical data is presented which examines the extent to which a varying number of IDDQ tests can detect parts which would fail stuck-at tests. This leads to development of a composite metric, based on stuck-at coverage, which allows a tradeoff to be made between adding further logic tests and adding IDDQ tests.
Index Terms:
application specific integrated circuits; fault diagnosis; logic testing; integrated circuit testing; CMOS logic circuits; automatic testing; IDDQ testing; stuck-at coverage situations; IC testing; quality goal; graded coverage; composite metric; logic tests; ASIC
Citation:
P.C. Maxwell, "The use of IDDQ testing in low stuck-at coverage situations," vts, pp.0084, 13th IEEE VLSI Test Symposium (VTS'95), 1995
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