A low cost 100 MHz analog test bus

	This Article
	Subscribers, please Login Purchase article: $19 PDF IEEE Xplore Subscribers RSS feed
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan/Endnote
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by S. Sunter

13th IEEE VLSI Test Symposium (VTS'95)

Princeton, New Jersey

April 30-May 03

ISBN: 0-8186-7000-2

	ASCII Text	x
	S. Sunter, "A low cost 100 MHz analog test bus," VLSI Test Symposium, IEEE, pp. 0060, 13th IEEE VLSI Test Symposium (VTS'95), 1995.

	BibTex	x
	@article{ 10.1109/VTEST.1995.512618, author = {S. Sunter}, title = {A low cost 100 MHz analog test bus}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {1995}, isbn = {0-8186-7000-2}, pages = {0060}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.1995.512618}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Test Symposium, IEEE TI - A low cost 100 MHz analog test bus SN - 0-8186-7000-2 SP EP A1 - S. Sunter, PY - 1995 KW - mixed analogue-digital integrated circuits; integrated circuit design; design for testability; capacitance; analog test bus; on-chip analog bus; digital three-state inverter; low-input capacitance; signal bandwidth; bus input; IC design; DFT; mixed-signal circuits; 100 MHz VL - 0 JA - VLSI Test Symposium, IEEE ER -

S. Sunter, Telecom Microelectron. Centre, Northern Telecom Electron. Ltd., Nepean, Ont., Canada

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTEST.1995.512618

Abstract: This paper describes an on-chip analog bus whose bandwidth is limited primarily by an off-chip amplifier. It uses only a digital 3-state inverter for each bus input. The high-speed and constant low-input capacitance of this scheme make it suitable for measuring sensitive or even digital signals. For equal silicon area, the signal bandwidth is demonstrated to be 10 to 40 times that of previously reported transmission gate schemes.

Index Terms:

mixed analogue-digital integrated circuits; integrated circuit design; design for testability; capacitance; analog test bus; on-chip analog bus; digital three-state inverter; low-input capacitance; signal bandwidth; bus input; IC design; DFT; mixed-signal circuits; 100 MHz

Citation:

S. Sunter, "A low cost 100 MHz analog test bus," vts, pp.0060, 13th IEEE VLSI Test Symposium (VTS'95), 1995

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.