Testing combinational iterative logic arrays for realistic faults

V
VTS
1995
13th IEEE VLSI Test Symposium (VTS'95)
Abstract - Testing combinational iterative logic arrays for realistic faults

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13th IEEE VLSI Test Symposium (VTS'95)

Princeton, New Jersey

April 30-May 03

ISBN: 0-8186-7000-2

	ASCII Text	x
	D. Gizopoulos, D. Nikolos, A. Paschalis, "Testing combinational iterative logic arrays for realistic faults," VLSI Test Symposium, IEEE, pp. 0035, 13th IEEE VLSI Test Symposium (VTS'95), 1995.

	BibTex	x
	@article{ 10.1109/VTEST.1995.512614, author = {D. Gizopoulos and D. Nikolos and A. Paschalis}, title = {Testing combinational iterative logic arrays for realistic faults}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {1995}, isbn = {0-8186-7000-2}, pages = {0035}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.1995.512614}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Test Symposium, IEEE TI - Testing combinational iterative logic arrays for realistic faults SN - 0-8186-7000-2 SP EP A1 - D. Gizopoulos, A1 - D. Nikolos, A1 - A. Paschalis, PY - 1995 KW - combinational circuits; fault diagnosis; logic testing; logic arrays; cellular arrays; VLSI; integrated circuit testing; combinational iterative logic arrays; realistic faults; two-dimensional logic arrays; one-dimensional logic arrays; n-pattern tests; C-testability; linear-testability; cell fault model; efficient test set; ILA VL - 0 JA - VLSI Test Symposium, IEEE ER -

D. Gizopoulos, Inst. of Informatics & Telecommun., NCSR Demokritos, Attiki, Greece

D. Nikolos, Inst. of Informatics & Telecommun., NCSR Demokritos, Attiki, Greece

A. Paschalis, Inst. of Informatics & Telecommun., NCSR Demokritos, Attiki, Greece

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTEST.1995.512614

Abstract: In this paper we give the fundamental theory for testing one or two-dimensional Iterative Logic Arrays (ILAs) with respect to realistic faults requiring two-pattern or generally n-pattern tests. We give conditions so that C-testability and linear-testability are preserved. According to our approach the extensive work made for ILAs under the Cell Fault Model can be easily used to derive an efficient test set of an ILA for more realistic faults.

Index Terms:

combinational circuits; fault diagnosis; logic testing; logic arrays; cellular arrays; VLSI; integrated circuit testing; combinational iterative logic arrays; realistic faults; two-dimensional logic arrays; one-dimensional logic arrays; n-pattern tests; C-testability; linear-testability; cell fault model; efficient test set; ILA

Citation:

D. Gizopoulos, D. Nikolos, A. Paschalis, "Testing combinational iterative logic arrays for realistic faults," vts, pp.0035, 13th IEEE VLSI Test Symposium (VTS'95), 1995

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