State-of-the-art FPGA architectures have millions of gates in CLBs, Block RAMs, and Multiplier blocks which can host fairly large designs. While their physical design calls for floorplanning, the traditional algorithm for ASIC do not suffice. In this paper, we have proposed an algorithm for unified floorplan topology generation and sizing for recent heterogeneous FPGAs. Experimental results on a set of benchmark circuits show that our three step floorplan generation method can produce feasible solutions very fast with 45% improvement in total half perimeter wirelength compared to the very few previous approaches.