20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07) Fault Coverage and Fault Efficiency of Transistor Shorts using Gate-Level Simulation and Test Generation Bangalore, India January 06-January 10 ISBN: 0-7695-2762-0
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VLSID.2007.83
This paper proposes a theory of transistor short faults and their detection in logic test environment. We define transistor short models, and reveal the characteristics of equivalent faults and redundant faults. Also, we present a stuck-at fault simulation method and a test generation method that uses only the gate-level description of the circuits while dealing with transistor short faults. We present experimental results for ISCAS benchmark circuits to demonstrate the effectiveness of the methodology proposed in this paper.
Citation:
Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Yuzo Takamatsu, "Fault Coverage and Fault Efficiency of Transistor Shorts using Gate-Level Simulation and Test Generation," vlsid, pp.781-786, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07), 2007 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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