A 2.5Gbps Quad CMOS Transceiver Cell Using Regulated Supply Low Jitter PLL

V
VLSID
2007
20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07)
Abstract - A 2.5Gbps Quad CMOS Transceiver Cell Using Regulated Supply Low Jitter PLL

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	Similar Articles Articles by Vijay Khawshe Articles by Pravin V Kumar Articles by Renu Rangnekar Articles by Kapil Vyas Articles by Kashi Prabu Articles by Mahabaleshwara Articles by Manish Jain Articles by Navin Mishra Articles by Abhijit Abhyankar

20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07)

Bangalore, India

January 06-January 10

ISBN: 0-7695-2762-0

	ASCII Text	x
	Vijay Khawshe, Pravin V Kumar, Renu Rangnekar, Kapil Vyas, Kashi Prabu, Mahabaleshwara , Manish Jain, Navin Mishra, Abhijit Abhyankar, "A 2.5Gbps Quad CMOS Transceiver Cell Using Regulated Supply Low Jitter PLL," VLSI Design, International Conference on, pp. 141-145, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07), 2007.

	BibTex	x
	@article{ 10.1109/VLSID.2007.7, author = {Vijay Khawshe and Pravin V Kumar and Renu Rangnekar and Kapil Vyas and Kashi Prabu and Mahabaleshwara and Manish Jain and Navin Mishra and Abhijit Abhyankar}, title = {A 2.5Gbps Quad CMOS Transceiver Cell Using Regulated Supply Low Jitter PLL}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {2007}, issn = {1063-9667}, pages = {141-145}, doi = {http://doi.ieeecomputersociety.org/10.1109/VLSID.2007.7}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - A 2.5Gbps Quad CMOS Transceiver Cell Using Regulated Supply Low Jitter PLL SN - 1063-9667 SP141 EP145 A1 - Vijay Khawshe, A1 - Pravin V Kumar, A1 - Renu Rangnekar, A1 - Kapil Vyas, A1 - Kashi Prabu, A1 - Mahabaleshwara , A1 - Manish Jain, A1 - Navin Mishra, A1 - Abhijit Abhyankar, PY - 2007 KW - null VL - 0 JA - VLSI Design, International Conference on ER -

Vijay Khawshe, Rambus Bangalore, India

Pravin V Kumar, Rambus Bangalore, India

Renu Rangnekar, Rambus Bangalore, India

Kapil Vyas, Rambus Bangalore, India

Kashi Prabu, Rambus Bangalore, India

Mahabaleshwara, Rambus Bangalore, India

Manish Jain, Rambus Bangalore, India

Navin Mishra, Rambus Bangalore, India

Abhijit Abhyankar, Rambus Bangalore, India

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VLSID.2007.7

A 2.5 Gbps serial link is fabricated in TSMC 90nm process. The link is targeted to support various serial link standards. To maintain a constant transmit swing the link supports automatic calibration for the on die termination (ODT) and bias, which supplies the driver. The self biased [1] regulated PLL dual loop architecture based on [2] is used which minimizes the clock jitter. A replica compensated regulator [3] is used in the PLL which cancels both the high frequency and low frequency components of the noise without affecting the PLL loop stability. A clock and data recovery circuits based on 2x over sampling [4] is implemented inside each individual lane of the serial link. The cell consumes 350mW at 2.5Gbps with transmitted jitter of 44.5ps pk-pk.

Citation:

Vijay Khawshe, Pravin V Kumar, Renu Rangnekar, Kapil Vyas, Kashi Prabu, Mahabaleshwara , Manish Jain, Navin Mishra, Abhijit Abhyankar, "A 2.5Gbps Quad CMOS Transceiver Cell Using Regulated Supply Low Jitter PLL," vlsid, pp.141-145, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07), 2007

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