System level design is becoming the major design methodology for System-on-a-chip (SOC) design with IP (Intellectual Property) reuse to solve the productivity gap problem. How to synthesis efficient hardware from high level specifications, such as Java, SystemC or C++, is becoming an important issue. This paper presents a novel methodology to extract pipeline stages from high level behavioral models to improve performance. A set of self-timed pipeline modules is designed and implemented for constructing these pipeline stages. The preliminary experimental result shows that, when the Summation/Modular Multiplication is partitioned into two pipelined stages, the pipelined Summation/Modular Multiplication is 1.94/1.61 times faster than the non-pipelined version with 15.8%/1.8% hardware overhead.