20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07) Design and Testing of an Integrated Circuit for Multi-Electrode Neural Recording Bangalore, India January 06-January 10 ISBN: 0-7695-2762-0
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VLSID.2007.63
We have developed a single-chip neural recording system with wireless power delivery and telemetry. The 0.5-?m CMOS IC is designed to be bonded to the back of a 100-channel Utah Electrode Array. A pad near each amplifier allows connection of the chip to the MEMS electrode array. The complete Integrated Neural Interface will receive power wirelessly through a 2.64-MHz inductive link. A clock, regulated supply, and commands are derived from the power signal .The neural amplifiers each have a gain of 60 dB. A 10-bit charge-redistribution ADC is used to digitize the signal from one amplifier selected with an analog MUX. Digitizing all channels simultaneously would generate prohibitively high data rates; therefore, we perform data reduction by incorporating one-bit ?gspike detectors h into each amplifier. Neural data is transmitted off chip using an -integrated 433-MHz FSK transmitter. The chip measures 4.7 5.9 mm2 and consumes 13.5 mW of power.
Citation:
Reid R. Harrison, Paul T. Watkins, Ryan J. Kier, Daniel J. Black, Robert O. Lovejoy, Richard A. Normann, Florian Solzbacher, "Design and Testing of an Integrated Circuit for Multi-Electrode Neural Recording," vlsid, pp.907-912, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07), 2007 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||