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20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07)
Delay-Balanced Smart Repeaters for On-Chip Global Signaling
Bangalore, India
January 06-January 10
ISBN: 0-7695-2762-0
ASCII Text
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Roshan Weerasekera, Dinesh Pamunuwa, Li-Rong Zheng, Hannu Tenhunen, "Delay-Balanced Smart Repeaters for On-Chip Global Signaling," VLSI Design, International Conference on, pp. 308-313, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07), 2007.
 
 
BibTex
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@article{ 10.1109/VLSID.2007.62,
author = {Roshan Weerasekera and Dinesh Pamunuwa and Li-Rong Zheng and Hannu Tenhunen},
title = {Delay-Balanced Smart Repeaters for On-Chip Global Signaling},
journal ={VLSI Design, International Conference on},
volume = {0},
year = {2007},
issn = {1063-9667},
pages = {308-313},
doi = {http://doi.ieeecomputersociety.org/10.1109/VLSID.2007.62},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Design, International Conference on
TI - Delay-Balanced Smart Repeaters for On-Chip Global Signaling
SN - 1063-9667
SP308
EP313
A1 - Roshan Weerasekera,
A1 - Dinesh Pamunuwa,
A1 - Li-Rong Zheng,
A1 - Hannu Tenhunen,
PY - 2007
KW - null
VL - 0
JA - VLSI Design, International Conference on
ER -
 
Roshan Weerasekera, KTH School for Information and Communication Technology, Sweden
Dinesh Pamunuwa, Lancaster University, Lancaster LA1 4YR, United Kingdom
Li-Rong Zheng, KTH School for Information and Communication Technology, Sweden
Hannu Tenhunen, KTH School for Information and Communication Technology, Sweden
In this paper we propose a smart driver, whose drive strength is dynamically altered depending on the relative bit pattern, by partitioning it into a Main Driver and Assistant Driver. For a higher effective load capacitance both drivers switch, while for a lower effective capacitance the assistant driver is quiet. It is shown that in an UMC 0.18?m technology the potential peak power saving, for typical global wire lengths, can be as much 18% with a 12% jitter reduction over a traditional repeater for a data rate of 1Gb/s.
Citation:
Roshan Weerasekera, Dinesh Pamunuwa, Li-Rong Zheng, Hannu Tenhunen, "Delay-Balanced Smart Repeaters for On-Chip Global Signaling," vlsid, pp.308-313, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07), 2007
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