Delay Test Scan Flip-Flop: DFT for High Coverage Delay Testing

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	Similar Articles Articles by Gefu Xu Articles by Adit D. Singh

20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07)

Bangalore, India

January 06-January 10

ISBN: 0-7695-2762-0

	ASCII Text	x
	Gefu Xu, Adit D. Singh, "Delay Test Scan Flip-Flop: DFT for High Coverage Delay Testing," VLSI Design, International Conference on, pp. 763-768, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07), 2007.

	BibTex	x
	@article{ 10.1109/VLSID.2007.61, author = {Gefu Xu and Adit D. Singh}, title = {Delay Test Scan Flip-Flop: DFT for High Coverage Delay Testing}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {2007}, issn = {1063-9667}, pages = {763-768}, doi = {http://doi.ieeecomputersociety.org/10.1109/VLSID.2007.61}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - Delay Test Scan Flip-Flop: DFT for High Coverage Delay Testing SN - 1063-9667 SP763 EP768 A1 - Gefu Xu, A1 - Adit D. Singh, PY - 2007 KW - null VL - 0 JA - VLSI Design, International Conference on ER -

Gefu Xu, Auburn University, AL

Adit D. Singh, Auburn University, AL

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VLSID.2007.61

Scan based delay testing is currently mostly implemented using launch-on-capture (LOC) delay tests. Launch-on-shift (LOS) tests are generally more effective, achieving higher fault coverage with significantly fewer test vectors, but require a fast scan enable, which is not supported by most designs. We present a low cost solution for implementing LOS tests by adding a small amount of logic (six transistors) in each flip-flop to align the slow scan enable signal to the clock edge. Our new design can support full LOS and LOC testing, achieving an average TDF coverage of 92.67% in this combined mode for the ISCAS89 benchmarks. Adding a second slow global scan enable signal also allows mixed LOC/LOS tests, which can further increase coverage up to 94.86% on average for ISCAS89 benchmarks.

Citation:

Gefu Xu, Adit D. Singh, "Delay Test Scan Flip-Flop: DFT for High Coverage Delay Testing," vlsid, pp.763-768, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07), 2007

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