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20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07)
Architecture and Clock Programmable Baseband of an 800 MHz-6 GHz Software-Defined Wireless Receiver
Bangalore, India
January 06-January 10
ISBN: 0-7695-2762-0
ASCII Text
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R. Bagheri, A. Mirzaei, S. Chehrazi, A. A. Abidi, "Architecture and Clock Programmable Baseband of an 800 MHz-6 GHz Software-Defined Wireless Receiver," VLSI Design, International Conference on, pp. 135-140, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07), 2007.
 
 
BibTex
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@article{ 10.1109/VLSID.2007.42,
author = {R. Bagheri and A. Mirzaei and S. Chehrazi and A. A. Abidi},
title = {Architecture and Clock Programmable Baseband of an 800 MHz-6 GHz Software-Defined Wireless Receiver},
journal ={VLSI Design, International Conference on},
volume = {0},
year = {2007},
issn = {1063-9667},
pages = {135-140},
doi = {http://doi.ieeecomputersociety.org/10.1109/VLSID.2007.42},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Design, International Conference on
TI - Architecture and Clock Programmable Baseband of an 800 MHz-6 GHz Software-Defined Wireless Receiver
SN - 1063-9667
SP135
EP140
A1 - R. Bagheri,
A1 - A. Mirzaei,
A1 - S. Chehrazi,
A1 - A. A. Abidi,
PY - 2007
KW - null
VL - 0
JA - VLSI Design, International Conference on
ER -
 
R. Bagheri, University of California, Los Angeles
A. Mirzaei, University of California, Los Angeles
S. Chehrazi, University of California, Los Angeles
A. A. Abidi, University of California, Los Angeles
A software-defined radio receiver is designed from a low power ADC perspective, exploiting programmability of windowed integration sampler and clock-programmable discrete-time analog filters. To cover the major frequency bands in today use a wideband RF front-end, including the low noise amplifier and a wide tuning-range synthesizer, spanning over 800 MHz-6 GHz is designed. The entire receiver circuits are implemented in 90 nm CMOS technology. Programmability of the receiver is tested for GSM and 802.11g standards.
Citation:
R. Bagheri, A. Mirzaei, S. Chehrazi, A. A. Abidi, "Architecture and Clock Programmable Baseband of an 800 MHz-6 GHz Software-Defined Wireless Receiver," vlsid, pp.135-140, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07), 2007
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