20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07) Application of DC Analyzer to Combinatorial Optimization Problems Bangalore, India January 06-January 10 ISBN: 0-7695-2762-0
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VLSID.2007.39
Solution of many combinatorial optimization problems can be found by analyzing appropriate electrical networks made up of positive resistors, voltage sources, current sources and ideal diodes. This method is an alternative approach for the approximate solution of such problems. Two Graph method based fast simulator is a more suitable option for this purpose than Modified Nodal Analysis based conventional simulators. Using this approach we have made an attempt to solve min cost flow and single source shortest path problems. A planar min cost flow problem of size 200; 000 nodes and 600; 000 edges is solved by our simulator approximately within 0:1% of the optimum solution in about 11 mins. We have exactly solved a planar single source shortest path problem (having negative edge weights also) of size 100; 000 nodes and 600; 000 edges in about 2 mins. We have performed our experiments on a PIV processor having 1 GB RAM.
Citation:
Gaurav Trivedi, Sumit Punglia, H. Narayanan, "Application of DC Analyzer to Combinatorial Optimization Problems," vlsid, pp.869-874, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07), 2007 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||