20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07) AHIR: A Hardware Intermediate Representation for Hardware Generation from High-level Programs Bangalore, India January 06-January 10 ISBN: 0-7695-2762-0
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VLSID.2007.28
We present AHIR, an intermediate representation (IR), that acts as a transition layer between software compilation and hardware synthesis. Such a transition layer is intended to take advantage of optimisations available in the software compiler flow, and also to provide freedom to the low-level synthesiser, to explore options for application-specific implementations. Two operations become possible - reuse of computational resources across different modules in the design, and generation of an application-specific memory subsystem for faster data accesses. AHIR presents a decoupled view of the program, in terms of control flow, data flow and memory accesses. Each module in AHIR is a triplet consisting of a control-path, datapath and a symbolic association between the two. Memory is represented only by load-store operators, while the memory subsystem is separately designed by the implementor. In the program-to-hardware flow, a module in AHIR corresponds to a function in C. A complete program is a callgraph of functions, which is translated to a set of modules. The call-graph is restricted to be a DAG; recursion is not allowed. The representation is generated by a back-end in the software compiler, which runs after all source-level optimisations have been performed by relevant passes.
Citation:
Sameer D. Sahasrabuddhe, Hakim Raja, Kavi Arya, Madhav P. Desai, "AHIR: A Hardware Intermediate Representation for Hardware Generation from High-level Programs," vlsid, pp.245-250, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07), 2007 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||