20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07) A Reduced Complexity Algorithm for Minimizing N-Detect Tests Bangalore, India January 06-January 10 ISBN: 0-7695-2762-0
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VLSID.2007.24
We give a new recursive rounding linear programming (LP) solution to the problem of N-detect test minimzation. This is a polynomial- time solution that closely approximates the exact but NP-hard integer linear programming (ILP) solution. In ILP, a test is represented by a [0; 1] integer variable and the sum of those variables is minimized. Constraints ensure that each fault has at least N tests with non-zero variables. Tra- ditionally, the problem has been transformed to less complex LP by treating the variables as real numbers, regarded as probabilities with which they can be rounded o to 0 or 1. This is known as the randomized rounding method. In the new method, the LP is recursively used, each time rounding the largest variable to 1 and reducing the size of the LP. The method is found to converge to a solution in just a few LP runs and the result is usually better than that of randomized rounding. Experimental results include ISCAS85 benchmarks and a set of multiplier circuits. N-detect tests for N = 1; 5 and 15 are considered. Also, a 10-vector single-detect sequence for c6288 is given.
Citation:
Kalyana R. Kantipudi, Vishwani D. Agrawal, "A Reduced Complexity Algorithm for Minimizing N-Detect Tests," vlsid, pp.492-497, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07), 2007 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||