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20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07)
A Power and Area Efficient Maximum Likelihood Detector Implementation for High Throughput MIMO Systems
Bangalore, India
January 06-January 10
ISBN: 0-7695-2762-0
ASCII Text
x 
 
J.H Han, A.T Erdogan, T. Arslan, "A Power and Area Efficient Maximum Likelihood Detector Implementation for High Throughput MIMO Systems," VLSI Design, International Conference on, pp. 756-762, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07), 2007.
 
 
BibTex
x
 
@article{ 10.1109/VLSID.2007.22,
author = {J.H Han and A.T Erdogan and T. Arslan},
title = {A Power and Area Efficient Maximum Likelihood Detector Implementation for High Throughput MIMO Systems},
journal ={VLSI Design, International Conference on},
volume = {0},
year = {2007},
issn = {1063-9667},
pages = {756-762},
doi = {http://doi.ieeecomputersociety.org/10.1109/VLSID.2007.22},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Design, International Conference on
TI - A Power and Area Efficient Maximum Likelihood Detector Implementation for High Throughput MIMO Systems
SN - 1063-9667
SP756
EP762
A1 - J.H Han,
A1 - A.T Erdogan,
A1 - T. Arslan,
PY - 2007
KW - null
VL - 0
JA - VLSI Design, International Conference on
ER -
 
J.H Han, University of Edinburgh, UK
A.T Erdogan, University of Edinburgh, UK
T. Arslan, Institute of System Level Integration, Livingston, UK
A maximum likelihood detector (MLD) is presented for 4x4 QPSK Multiple-input multiple-output (MIMO) systems. A hybrid methodology combining precomputation of norm values followed with the transformation of the maximum likelihood algorithm is applied in order to achieve an efficient MLD implementation, in which 16 norm values are concurrently computed for high throughput while maintaining power and area efficiency. The MLD implementation results are compared with a conventional MLD in area and power. Simulation results demonstrate that the proposed MLD can achieve up to 74 Mbps throughput at a clock speed of 14 7MHz.
Citation:
J.H Han, A.T Erdogan, T. Arslan, "A Power and Area Efficient Maximum Likelihood Detector Implementation for High Throughput MIMO Systems," vlsid, pp.756-762, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07), 2007
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